Verilog

Verilog - Wikipedia, the free encyclopedia
Verilog HDL, not to be confused with VHDL, is most commonly used in the design, ... The designers of Verilog wanted a language with syntax similar to the C ...
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Verilog is a hardware description language (HDL) used to model Electronics#Electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of Analog circuit, Digital circuit, and Mixed-signal integrated circuits at various levels of Abstraction (computer science).

The designers of Verilog wanted a language with syntax similar to the C (programming language) so that it would be familiar to engineers and readily accepted. The language is case-sensitive, has a preprocessor like C, and the major control flow Keyword (computer programming)s, such as "if" and "while", are similar. The formatting mechanism in the printing routines and language Operator (programming) and their Operator precedence are also similar.

The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to define a block of code. The definition of constants in Verilog require a bit width along with their base, consequently these differ. Verilog 95 and 2001 don't have structures, pointers, or recursive subroutines, however SystemVerilog now includes these capabilities. Finally, the concept of time —so important to a HDL— won't be found in C.

The language differs from a conventional programming language in that the execution of Statement (programming) is not strictly linear. A Verilog design consists of a hierarchy of modules. Modules are defined with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires and registers. Concurrent and sequential statements define the behaviour of the module by defining the relationships between the ports, wires, and registers. Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But all concurrent statements and all begin/end blocks in the design are executed in parallel. A module can also contain one or more instances of another module to define sub-behavior.

A subset of statements in the language is logic synthesis. If the modules in a design contain only synthesizable statements, software can be used to transform or synthesize the design into a netlist that describes the basic components and connections to be implemented in hardware. The netlist may then be transformed into, for example, a form describing the standard cells of an integrated circuit (e.g. an Application-specific integrated circuit) or a bitstream for a programmable logic device (e.g. a FPGA).

History Beginning Verilog was invented by Phil Moorby and Prabhu Goel during the winter of 1983/1984 at Automated Integrated Design Systems (later renamed to Gateway Design Automation) in 1985 as a hardware modeling language. Gateway Design Automation was later purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators.

Verilog-95 With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Veriloginto the public domain under the Open Verilog International (OVI) (now known as Accellera)organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

Verilog 2001 Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed-operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the boolean-algebra to determine its correct value.) The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision-operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system-tasks. And finally, a few syntax additions were introduced to improve code-readability (eg. always @*, named-parameter override, C-style function/task/module header declaration.)

Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages.

Verilog 2005 Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword.)

A separate part of the Verilog standard , Verilog-AMS, attempts to integrate analog and mixed signal modelling with traditional Verilog.

SystemVerilog Systemverilog is a superset of Verilog-2005, with many new features and capabilities to aid design-verification and design-modeling.

The advent of High Level Verification languages such as OpenVera, and Verisity's E language encouraged the development of Superlog by Co-Design Automation Inc. Co-Design Automation Inc was later purchased by Synopsys. The foundations of Superlog and Vera were donated to Accellera, which later became the IEEE standard P1800-2005: SystemVerilog.

Example A hello world program looks like this:module main; initial begin $display("Hello world!"); $finish; end endmodule

A simple example of two Flip-flop (electronics) follows:module toplevel(clock,reset);input clock; input reset;

reg flop1; reg flop2;

always @ (posedge reset or posedge clock) if (reset) begin flop1